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| 0 R XC17V00 Series Configuration PROM 0 8 DS073 (v1.0) July 26, 2000 Advance Product Specification Features * One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices Simple interface to the FPGA; configurable to use a one user I/O pin Cascadable for storing longer or multiple bitstreams Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions Supports fast configuration Low-power CMOS Floating Gate process 3.3V supply voltage Available in compact plastic packages: VQ44, PC44, PC20, VO8, and SO20 Programming support by leading programmer manufacturers. Design support using the Xilinx Alliance and Foundation series software packages. Dual configuration modes for the XC17V16 and XC17V08 * Serial slow/fast configuration (up to 33 MHz) Parallel (up to 264 MHz) Description Xilinx introduces the high-density XC17V00 family of configuration PROMs which provide an easy-to-use, cost-effective method for storing large Xilinx FPGA configuration bitstreams. Initial devices in the 3.3V family are available in 16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal. When the FPGA is in SelectMAP mode, an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data are available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK. SelectMAP does not utilize a Length Count, so a free-running oscillator may be used. See Figure 3. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers. * * * * * * * * * * Guaranteed 20 year life data retention (c) 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS073 (v1.0) July 26, 2000 Advance Product Specification www.xilinx.com 1-800-255-7778 1 XC17V00 Series Configuration PROM R VCC VPP GND RESET/ OE or OE/ RESET CE CEO CLK Address Counter TC EPROM Cell Matrix Output OE DATA DS073_01_072600 Figure 1: Simplified Block Diagram for XC17V04, XC17V02, and XC17V01 (does not show programming circuit) VCC VPP GND RESET/ OE or OE/ RESET CE CEO CLK Address Counter TC BUSY EPROM Cell Matrix Output 8 OE D0 Data (Serial or Parallel Mode) 7 7 D[1:7] (SelectMAP Interface) DS073_02_072600 Figure 2: Simplified Block Diagram for XC17V16 and XC17V08 (does not show programming circuit) 2 www.xilinx.com 1-800-255-7778 DS073 (v1.0) July 26, 2000 Advance Product Specification R XC17V00 Series Configuration PROM Pin Description DATA[0:7] Data output is in a high-impedance state when either CE or OE are inactive. During programming, the D0 pin is I/O. Note that OE can be programmed to be either active High or active Low. Note: XC17V04, XC17V02, and XC17V01 have serial output only. BUSY (XC17V16 and XC17V08 only) If BUSY pin is floating, the user must program the BUSY bit which will cause BUSY pin to go Low internally. When asserted High, output data are held and when BUSY pin goes Low, data output will resume. VPP Programming voltage. No overshoot above the specified max voltage is permitted on this pin. For normal read operation, this pin must be connected to VCC. Failure to do so may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not leave VPP floating! CLK Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active. RESET/OE When High, this input holds the address counter reset and puts the DATA output in a high-impedance state. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at "0", and puts the DATA output in a high-impedance state. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be driven by the FPGAs INIT pin. The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW-130 Programmer. Third-party programmers have different methods to invert this pin. VCC and GND Positive supply and ground pins. PROM Pinouts for XC17V16 and XC17V08 Pin Name BUSY D0 D1 D2 D3 D4 D5 D6 D7 CLK RESET/OE (OE/RESET) CE GND CEO VPP VCC 44-pin VQFP 24 40 29 42 27 9 25 14 19 43 13 15 6, 18, 28, 27, 41 21 35 8, 16, 17, 26, 36, 38 44-pin PLCC 30 2 35 4 33 15 31 20 25 5 19 21 3, 12, 24, 34, 43 27 41 14, 22, 23, 32, 42, 44 CE When High, this pin disables the internal address counter, puts the DATA output in a high-impedance state, and forces the device into low-ICC standby mode. CEO Chip Enable output, to be connected to the CE input of the next PROM in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low. Capacity Devices XC17V16 XC17V08 Configuration Bits 16,777,216 8,388,608 DS073 (v1.0) July 26, 2000 Advance Product Specification www.xilinx.com 1-800-255-7778 3 XC17V00 Series Configuration PROM R PROM Pinouts for XC17V04, XC17V02, and XC17V01 Pin Name DATA CLK RESET/OE (OE/RESET) CE GND CEO VPP VCC 8-pin 20-pin VOIC SOIC 1 2 3 4 5 6 7 8 1 3 8 10 11 13 18 20 20-pin PLCC 2 4 6 8 10 14 17 20 44-pin VQFP 40 43 13 15 18, 41 21 35 38 44-pin PLCC 2 5 19 21 24, 3 27 41 44 Xilinx FPGAs and Compatible PROMs Device XCV600E XCV812E XCV1000E XCV1600E XCV2000E XCV2600E XCV3200E Configuration Bits 3,961,632 6,519,648 6,587,520 8,308,992 10,159,648 12,922,336 16,283,712 PROM XC17V04 XC17V08 XC17V08 XC17V08 XC17V16 XC17V16 XC17V16 Notes: 1. The suggested PROM is determined by compatibility with the higher configuration frequency of the Xilinx FPGA CCLK. Controlling PROMs Connecting the FPGA device with the PROM. Configuration Bits 4,194,304 2,701,312 1,679,360 * * * * The DATA output(s) of the of the PROM(s) drives the DIN input of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the PROM(s). The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The RESET/OE input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. Other methods--such as driving RESET/OE from LDC or system reset--assume the PROM internal power-on-reset is always in step with the FPGA's internal power-on-reset. This may not be a safe assumption. The PROM CE input can be driven from either the LDC or DONE pins. Using LDC avoids potential contention on the DIN pin. The CE input of the lead (or only) PROM is driven by the DONE output of the lead FPGA device, provided that DONE is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum. SelectMAP mode is similar to Slave Serial mode. The DATA is clocked out of the PROM one byte per CCLK instead of one bit per CCLK cycle. See FPGA data sheets for special configuration requirements. Capacity Devices XC17V04 XC17V02 XC17V01 Xilinx FPGAs and Compatible PROMs Device XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000 XCV50E XCV100E XCV200E XCV300E XCV400E XCV405E Configuration Bits 559,200 781,216 1,040,096 1,335,840 1,751,808 2,546,048 3,607,968 4,715,616 6,127,744 630,048 863,840 1,442,106 1,875,648 2,693,440 3,340,400 PROM XC17V01 XC17V01 XC17V01 XC17V01 XC17V02 XC17V02 XC17V04 XC17V08 XC17V08 XC17V01 XC17V01 XC17V01 XC17V02 XC17V02 XC17V04 * * * 4 www.xilinx.com 1-800-255-7778 DS073 (v1.0) July 26, 2000 Advance Product Specification R XC17V00 Series Configuration PROM unchanged after configuration is complete. Therefore, to reprogram the FPGA with another program, the DONE line is pulled Low and configuration begins at the last value of the address counters. This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and then restarts a new configuration, as intended, but the PROM does not reset its address counter, since it never saw a High level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the FPGA is the master, it issues the necessary number of CCLK pulses, up to 16 million (224) and DONE goes High. However, the FPGA configuration will be completely wrong, with potential contentions inside the FPGA and on its output pins. This method must, therefore, never be used when there is any chance of external reset during configuration. FPGA Master Serial Mode Summary The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. The Xilinx PROMs have been designed for compatibility with the Master Serial mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode-select pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during configuration. Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are required to configure an FPGA. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this automatically with an on-chip default pull-up resistor. Cascading Configuration PROMs For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded PROMs provide additional memory. After the last bit from the first PROM is read, the next clock signal to the PROM asserts its CEO output Low and disables its DATA line. The second PROM recognizes the Low level on its CE input and enables its DATA output. See Figure 3. After configuration is complete, the address counters of all cascaded PROMs are reset if the FPGA RESET pin goes Low, assuming the PROM reset polarity option has been inverted. To reprogram the FPGA with another program, the DONE line goes Low and configuration begins where the address counters had stopped. In this case, avoid contention between DATA and the configured I/O use of DIN. Programming the FPGA With Counters Unchanged Upon Completion When multiple FPGA-configurations for a single FPGA are stored in a PROM, the OE pin should be tied Low. Upon power-up, the internal address counters are reset and configuration begins with the first program stored in memory. Since the OE pin is held Low, the address counters are left DS073 (v1.0) July 26, 2000 Advance Product Specification www.xilinx.com 1-800-255-7778 5 XC17V00 Series Configuration PROM R DOUT OPTIONAL Daisy-chained FPGAs with different configurations VCC 4.7K VCC OPTIONAL Slave FPGAs with identical configurations Vcco Vcc FPGA Modes* ** VCC VCCO DATA BUSY First CLK PROM CEO CE OE/RESET BUSY DATA CLK CE Cascaded PROM DIN CCLK DONE INIT PROGRAM (Low Resets the Address Pointer) OE/RESET *For Mode pin connections, refer to the appropriate FPGA data sheet. **Virtex, Virtex-E is 300 ohms, all others are 4.7K. Master Serial Mode I/O* I/O* Modes*** CS WRITE 1K 1K VCC External Osc 3.3V 4.7K CLK 8 D[0:7] CE OE/RESET CEO VCC VCCO BUSY XC17Vxx VCC VCCO VIRTEX Select MAP BUSY CCLK D[0:7] DONE INIT ** *CS and WRITE must be pulled down to be used as I/O. One option is shown. **Virtex, Virtex-E is 300 ohms, all others are 4.7K. ***For Mode pin connections, refer to the appropriate FPGA data sheet. Virtex Select MAP Mode, XC17V16 and XC17V08 only. DS073_03_072600 Figure 3: (a) Master Serial Mode (b) Virtex SelectMAP Mode (dotted lines indicates optional connection) 6 www.xilinx.com 1-800-255-7778 DS073 (v1.0) July 26, 2000 Advance Product Specification R XC17V00 Series Configuration PROM Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input. Programming The devices can be programmed on programmers supplied by Xilinx or qualified third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device. Table 1: Truth Table for XC17V00 Control Inputs Control Inputs RESET Inactive Active Inactive Active CE Low Low High High Internal Address If address < TC(1): increment If address > TC(1): don't change Held reset Not changing Held reset DATA Active High-Z High-Z High-Z High-Z Outputs CEO High Low High High High ICC Active Reduced Active Standby Standby Notes: 1. The XC17V00 RESET input has programmable polarity 1. TC = Terminal Count = highest address value. TC + 1 = address 0. DS073 (v1.0) July 26, 2000 Advance Product Specification www.xilinx.com 1-800-255-7778 7 XC17V00 Series Configuration PROM R Absolute Maximum Ratings Symbol VCC VPP VIN VTS TSTG TSOL Description Supply voltage relative to GND Supply voltage relative to GND Input voltage relative to GND Voltage applied to High-Z output Storage temperature (ambient) Maximum soldering temperature (10s @ 1/16 in.) Conditions -0.5 to +7.0 -0.5 to +12.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 Units V V V V C C Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions (3V Supply) Symbol VCC(1) Description Supply voltage relative to GND (TA = 0C to +70C) Supply voltage relative to GND (TA = -40C to +85C) Notes: 1. During normal read operation VPP MUST be connect to VCC. Min Commercial Industrial 3.0 3.0 Max 3.6 3.6 Units V V DC Characteristics Over Operating Condition Symbol VIH VIL VOH VOL ICCA ICCS ICCA ICCS IL CIN COUT High-level input voltage Low-level input voltage High-level output voltage (IOH = -3 mA) Low-level output voltage (IOL = +3 mA) Supply current, standby mode (at maximum frequency) (XC17V16 and XC17V08 only) Supply current, standby mode (XC17V16, XC17V08, XC17V04, XC17V02 only) Supply current, standby mode (at maximum frequency) (XC17V04, XC17V02, and XC17V01 only) Supply current, standby mode (XC17V01 only) Input or output leakage current Input capacitance (VIN = GND, f = 1.0 MHz) Output capacitance (VIN = GND, f = 1.0 MHz) Description Min 2 0 2.4 -10 Max VCC 0.8 0.4 100 350 10 50 10 10 10 Units V V V V mA A mA A A pF pF 8 www.xilinx.com 1-800-255-7778 DS073 (v1.0) July 26, 2000 Advance Product Specification R XC17V00 Series Configuration PROM AC Characteristics Over Operating Condition for XC17V04, XC17V02, and XC17V01 CE TSCE TSCE THCE RESET/OE TLC THC THOE TCYC CLK TOE TCE TCAC TOH TDF DATA TOH DS073_04_072600 Symbol TOE TCE TCAC TDF TOH TCYC TLC THC TSCE THCE THOE OE to data delay CE to data delay CLK to data delay Description Min 0 67 25 25 25 0 25 Max 30 45 45 50 - Units ns ns ns ns ns ns ns ns ns ns ns CE or OE to data float delay(2,3) Data hold from CE, OE, or CLK(3) Clock periods CLK Low time(3) CLK High time(3) CE setup time to CLK (to guarantee proper counting) CE hold time to CLK (to guarantee proper counting) OE hold time (guarantees counters are reset) Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. DS073 (v1.0) July 26, 2000 Advance Product Specification www.xilinx.com 1-800-255-7778 9 XC17V00 Series Configuration PROM R AC Characteristics Over Operating Condition for XC17V16 and XC17V08 CE TSCE TSCE THCE RESET/OE TLC THC THOE TCYC CLK TOE TCE TCAC TOH TDF DATA TSBUSY THBUSY TOH BUSY DS073_05_072600 Symbol TOE TCE TCAC TDF TOH TCYC TLC THC TSCE THCE THOE TSBUSY THBUSY TWKU OE to data delay CE to data delay CLK to data delay(2) Description Min 0 67 25 25 25 0 25 5 5 100 Max 15 20 20 35 - Units ns ns ns ns ns ns ns ns ns ns ns ns ns ms CE or OE to data float delay(3,4) Data hold from CE, OE, or CLK(4) Clock periods CLK Low time(4) CLK High time(4) CE setup time to CLK (to guarantee proper counting) CE hold time to CLK (to guarantee proper counting) OE hold time (guarantees counters are reset) BUSY setup time BUSY hold time VCC reached normal supply voltage range to output valid Notes: 1. AC test load = 50 pF. 2. When BUSY = 0. 3. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 4. Guaranteed by design, not tested. 5. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 10 www.xilinx.com 1-800-255-7778 DS073 (v1.0) July 26, 2000 Advance Product Specification R XC17V00 Series Configuration PROM AC Characteristics Over Operating Condition When Cascading RESET/OE CE CLK TCDF DATA Last Bit TOCK CEO TOCE TOCE DS073_06_062800 First Bit TOOE Symbol TCDF TOCK TOCE TOOE Description CLK to data float delay(2,3) CLK to CEO delay(3) CE to CEO delay(3) RESET/OE to CEO delay(3) Min - Max 50 30 35 30 Units ns ns ns ns Notes: 1. AC test load = 50 pF 2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. DS073 (v1.0) July 26, 2000 Advance Product Specification www.xilinx.com 1-800-255-7778 11 XC17V00 Series Configuration PROM R Ordering Information XC17V16 PC44 C Device Number XC17V16 XC17V08 XC17V04 XC17V02 XC17V01 Package Type VQ44 PC44 V08 PC20 SO20 = = = = = 44-pin Plastic Quad Flat Package 44-pin Plastic Chip Carrier 8-pin Plastic Small Outline Thin Package 20-pin Plastic Leaded Chip Carrier 20-pin Plastic Small Outline Package Operating Range/Processing C = Commercial (TA = 0 to +70C) I = Industrial (TA = -40 to +85C) Valid Ordering Combinations XC17V16VQ44C XC17V16PC44C XC17V16VQ44I XC17V16PC44I XC17V08VQ44C XC17V08PC44C XC17V08VQ44I XC17V08PC44I XC17V04PC20C XC17V04PC44C XC17V04VQ44C XC17V04PC20I XC17V04PC44I XC17V04VQ44I XC17V02PC20C XC17V02PC44C XC17V02VQ44C XC17V02PC20I XC17V02PC44I XC17V02VQ44I XC17V01PC20C XC17V01VO8C XC17V01SO20C XC17V01PC20I XC17V01VO8I XC17V01SO20I Marking Information Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows: 17V16 PC44 C Device Number 17V16 17V08 17V04 17V02 17V01 Package Type VQ44 PC44 V08 PC20 SO20 = = = = = 44-pin Plastic Quad Flat Package 44-pin Plastic Chip Carrier 8-pin Plastic Small Outline Thin Package 20-pin Plastic Leaded Chip Carrier 20-pin Plastic Small Outline Package Operating Range/Processing C = Commercial (TA = 0 to +70C) I = Industrial (TA = -40 to +85C) Revision History The following table shows the revision history for this document. Date 07/26/00 Version 1.0 Initial Xilinx release. Revision 12 www.xilinx.com 1-800-255-7778 DS073 (v1.0) July 26, 2000 Advance Product Specification |
Price & Availability of XC17V00
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